Field of the Invention
The invention relates to a semiconductor structure and a method for manufacturing the same, and particularly relates to a three-dimensional package structure and a method for manufacturing the same.
Description of Related Art
In recent years, in order to increase applications of printed circuit board (PCB), the PCB is fabricated into a multi-layer circuit structure according to many techniques. A method for fabricating the multi-layer circuit structure is to construct a build-up structure by using copper foils or other suitable conductive materials and prepreg (PP) or other suitable dielectric materials, and repeatedly laminate the build-up structure for stacking on a core layer, so as to form the multi-layer circuit structure, by which an internal wiring space of the multi-layer circuit structure is increased. The conductive material on the build-up structure can construct a conductive circuit according to a required circuit layout, and blind holes or through holes of the build-up structure can be filled with a conductive material for conducting each of the layers. In this way, the number of the circuit layers of the multi-layer circuit structure can be adjusted according to an actual requirement, and the multi-layer circuit structure can be manufactured according to the above method.
However, since the prepreg or the other suitable dielectric material is relatively soft, a warpage issue of the multi-layer circuit structure is probably encountered during the manufacturing process thereof. When the above PCB is applied to a package-on-package (POP) structure, the POP structure may also have the warpage issue, by which a yield of the POP structure is decreased.